Parallel CRC generation in VHDL

Cyclic redundancy check values can be generated easily with a fed back shift register, when the user data appear as a sequel of bits. But often the data stream is organized in words of different sizes. Also in those cases, the CRC values can be generated with programmable logic. This is possible in a single clock cycle when suitable combinatorics is used.

The CRC type is determined by the following parameters:

- Polynom size = CRC size in bits

- the binary generator polynom

- the initial CRC value

- user data reverse or not reverse

- CRC reverse or not reverse

- final CRC inversion or not

Additionally,  the user data size must be defined, when a combinatorial solution for the parallel CRC generation is to be designed.

CRC type overview: Catalogue of parametrised CRC algorithms


The following principle is a proven solution for the CRC generation from a sequel of bytes :

crc16 <= CRC16_Initial;

loop (n++) for all data bytes

     crc16 <= NewCRC(crc16, DBYTE(n));

loop end

crc16 <= crc16 xor CRC16_Final;

The "NewCRC" function contains the parallel CRC combinatorics. This function and the constants  "CRC16_Initial" and "CRC16_Final" are CRC type depending. They are defined in a package, which is in a separate file in the project folder. Therefore, they can be included with the "work" library. The package file must be compiled first.


Click here to see, how the "NewCRC" function is used in a state machine.


For the CRC type depending development of the required combinatorics see here:

Parallel CRC Generation (IEEE Micro, Vol 10 Issue 5, September 1990)

A Practical Parallel CRC Generation Method (Circuit Cellar, January 2010) 

A Systematic Approach for Parallel CRC Computations (Journal of Information Science and Engineering 17, 2001



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